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Senior IC Design Engineer

156554
San Jose, CA, United States
May 7, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

Seeking individual who can contribute to the development of cutting edge design in Xilinx  FPGAs. Must be able to understand complex networks. Primary task would be to assist with block timing closure (STA) for multiple blocks. Working knowledge of PLLs a plus. Must be able to communicate well among team and with overseas groups. Should have experience in writing Primetime constraints, reading/writing Verilog RTL, schematic design and simulation, back end flows and working with verification/test groups. 

  • Expert in Synopsys Primetime
  • Knowledgeable in ICC2, Design Complier a plus
  • Ability to understand circuit design and write constraints to fully test
  • Capable of debugging runs and working with others to help improve runs
  • Willing to learn and work with internal tool flows
  • Good communication skills and ability to give feedback to designers on how to improve designs
  • Ability to communicate with architecture, RTL design and other remote teams
  • Primarily responsible for Timing Closure (STA) but willing to perform a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization, Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), DRC, LVS, Antenna checks, IR drop (RedHawk), multi voltage checks etc.
  • Participating in the development of a back-end SoC design flow.
  • Experience of UPF low power design
  • Previous experience clock generation circuitry a plus

Compliant Design Implementation

  • Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
  • Can run and implement designs (e.g., debugging, digital and analog design, circuit design, RTL signal flow, basic TCL coding, and timing tool basics)
  • Accurately documents and effectively communicates the rational for a design to design implementation stakeholders (e.g., peer reviews, Technical Solution Groups, management)
  • Coordinates with and manages external vendor deliverables
  • Mentors less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones

Education Requirements: Master’s degree in Computer Engineering, Electrical Engineering or related field with 4+ plus years of relevant experience.

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