At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.
This job opening is in the RTL Synthesis team which is part of FPGA Implementation software (FIS) group. FIS group is responsible for delivering state of the art synthesis, optimization, place and route technology for all Xilinx users. We are passionate about extending our leadership position through rapid innovation while maintaining high quality. The team comprises a set of highly skilled engineers who value innovation, quality and team spirit.
In this position, you are responsible for :
- Developing and maintaining best in class HDL compilers, Data flow optimizations and Logic Synthesis algorithms and flows
- Implementing and enhancing Xilinx FPGA specific optimization and mapping flows
- Interacting with IP development and delivery groups, advanced flow groups, Hardware architecture group, GUI group, application architects, and other EDA groups
Education and Experience Requirements
- BS in CS, EE, CE with 5+ years of relevant working experience, MS with 3+ years or related Ph.D. with 0 years of experience in software industry.
- Proven experience in developing state of the art in one or more of the following areas: HDL compilers, data flow graph optimizations, logic optimization and technology mapping algorithms for ASIC or FPGA synthesis tools is desirable.
- Hands on experience in working with standard data structures like BDDs, SAT solvers and timing analysis engines is desirable.
- Strong background in basic digital design principles, graph theory and data structures required.
- Familiarity with FPGA architectures and flows desirable.
- Fluent in C, C++, Unix shell scripts, Tcl and exposure to using Verilog/VHDL simulators and formal verification tools.
- Experience in developing and supporting large-scale software, including understanding usage model, writing functional specification, implementing code, testing, documentation, and providing customer support.
- Strong communication skills required. Ability to lead and coordinate discussions as well as making presentations in meetings.