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Design Engineer

156393
San Jose, CA, United States
Jan 8, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


We are looking for an individual to join the Communication & MAC IP COE Team as a Design Engineer.


As part of our team, you will contribute in the area of Hardware Emulation/Validation of these blocks. You will be part of a team that creates testcase designs in FPGAs to emulate the functionality of these blocks.  You will be involved in the silicon life-cycle from testing of emulated next-generation RTL through to silicon validation and characterization.


Responsibilities include:

  • Develop scripts using Python, Perl or other scripting languages to automate the tests and parse results
  • Perform validation and characterization of the embedded IP blocks in the lab across PVT and with protocol test equipment
  • Support the team in developing system level designs to validate functionality of the next generation wired and wireless blocks such as Ethernet MAC
  • Support the team in running the HDL code through LINT, CDC, Synthesis tools, etc.
  • Document use models and test cases
  • Maintain GIT or other repositories for all the hardware designs and software development
  • Support the team on both front-end and back-end design activities required to deliver the block


Qualifications:

This position requires an MS in Electrical Engineering or Computer Engineering.


Job Requirements:

  • Experience with Verilog or VHDL and Digital Design Principles
  • Knowledge of FPGA and its tool flow 
  • Experience in scripting in Python, Perl or other languages
  • Strong written and verbal skills
  • Strong debugging skills
  • Knowledge of lab equipment
  • Experience with computer architecture
  • Knowledge of embedded systems or ARM architecture
  • Knowledge of design EDA tools such as Synopsys or Cadence

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