Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
- Adapts design verification implementation methods to latest standards
- Develops customization scripts for local optimization
- Works effectively with evolving tool sets
- Development and Validation
- Prototypes and evaluates many competing implementations
- Exercises strong analytical problem solving in block-level verification
- Accurately documents and effectively communicates verification decisions and rationale
Iterative Component Verification and Validation
Process Adaptation and Optimization
- Supports Test Engineering in the setting up of valid test verification criteria and plans at the system level
- Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications in a timely manner
- Ensures seamless component integration, device manufacturability, and sign-off acceptability based on formal verification test data
- Mentors less experienced design engineers and leads experienced verification engineers in verification testing
Verification and Validation
- Provides design management (e.g., CAD department) on the efficiency of proposed methods
- Adopts and applies Xilinx formal, cross-COE process innovation to facilitate standardization and advance efficient time-to-market practices
- Adopts and applies Xilinx formal revision control
- Solid knowledge of required scripting and automation
- Mentors junior design engineers on emerging methods and how best to integrate these into practice
- Creates verification plans at the block level
- Understands protocols and standards associated with products
- Collaborates with program management to verify that components meet technical specifications and quality requirements (e.g., power efficiency, area efficiency, ease of use)
- Collaborates with other hardware and software groups to ensure effective component integration within the larger system
- Supports Test Engineering or customer verification engineering teams in the setting up of valid test verification criteria and plans
- Supports Applications Engineering in debugging customer issues
- Troubleshoots component blocks as required to ensure milestone achievement and production-ready integration (e.g., specifications, performance, standards)
- Manages regression suites for products, and contributes to the tool flow
- Acts on verification test data to ensure seamless component integration, device manufacturability, and sign-off acceptability if applicable (e.g., customer sample feedback, iterative tape-out production turns involving 3rd parties)
- When required, creates environment and infrastructure to test designs in a HW verification environment, and running test scenarios
- Solid understanding of FPGA building blocks and how they relate
- Provides input into feasibility studies for proposed features
- Understanding of customer tool flow and use models
- Design Enablement (Tools/System/Practice)
- Exercises technical innovation in the use of standard design implementation tools and methods (e.g., circuit techniques)
- Actively explores innovative design implementation tools or methods or their impact on implementation design practices (e.g., process excursions, boundary excess, signal passing of different voltages)
- Stays current with and proposes the internal use of industry approaches, algorithms, and practices
- Expert in technical innovation in the use of standard design implementation tools and methods (e.g. understands how to leverage the tool to have a positive impact on the design).
- Aggregates and provides inputs to tool developers and vendors on issues to improve the tools.
- Actively explores innovative design implementation tools or methods and their impact on implementation design practices and makes recommendations for tool acquisition (e.g., OVM and Questa)
- Stays current with and proposes the internal use of industry approaches, algorithms, and practices (e.g. state of the art DSP algorithms).
- Proposes the solution of FPGA-specific problems with tool vendors.
BS/MS EE, 6-10 yrs of relevant exp, 8+ years of design verification experience, inclusive of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions, Strong Familiarity with Verification Methodologies such as OVM, AVM, or VMM, Familiarity with Verilog and General Logic Design concepts, Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR3/DDR4/LPDDR3, Strong working knowledge of UNIX environment and scripting languages such as Perl or Python, Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim, Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla, Experience in verifying multimillion gate chip designs from specifications to tape-out.
SVA would be an added advantage.
8yrs – 10 Yrs