Join Xilinx’s Serdes Technology Team, this highly visible role, as part of a talented team you will help deliver High Quality Gigabit Transceivers
- The position requires thorough knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background:
- 2 to 5 years hands-on experience in ASIC timing constraints generation and timing closure
- Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and cross-talk effects on timing
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technologies
- Knowledge of timing corners/modes and process variations
- Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs
- Proficient in scripting languages Python, Perl and TCL
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).
- Self starter that is highly motivated
- Familiarity with RTL, synthesis, logic equivalence, and backend related methodology and tools
As a STG STA engineer, you will be a part of the Serdes digital design team responsible for providing integrated solutions. Responsibilities include: Block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) Develop and maintain methodology and flows related to timing verification and closure. Generation of timing constraints, analyze timing reports and utilize scripting techniques to develop insights that drive rapid timing closure. Support digital chip integration work and flows.
BSEE is required,. MSEE preferred.
Years of Experience