SerDes Architecture and Modeling Engineer

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

With the exponential growth in AI inference deployment, the state of the art in AI models are rapidly evolving and will continue for the foreseeable future. Domain-Specific Architectures are required for efficient AI inference. Only adaptable hardware platforms can provide efficient DSAs for the latest AI models. The Xilinx AI software platform makes Xilinx’s adaptable hardware accessible to all software and AI developers by providing a familiar programming interface and comprehensive libraries. The result is Real Time AI Inference up to 4X faster than GPUs and 10X less power than CPUs.

• Creating silicon and system level specifications
• Developing and verifying SerDes design models
• Developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.
• Channel modeling, IBIS-AMI model development, and system level simulations
• Behavioral modeling of different blocks in transceivers (FFE, CTLE, DFE, CDR, PLL, etc.)
• Adaptive signal processing, coding, and FEC algorithms
• Presenting design trade-off analysis and implementation recommendations with custom circuit designers

• BS with 3+ years of exp or MS with 1+ year of exp or PhD in Electrical Engineering, Computer Engineering or related equivalent 
• Experience in Signal modulation, coding, and FEC knowledge
• Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred
• Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.
• ADC based SerDes architecture experience is a plus
• Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus and familiarity with Simulink/Matlab and C/C++ programming
• Experience with lab equipment for high-speed digital systems
• Good understanding of high speed signal integrity issues
• Excellent technical communication skills (presentations and documentation)
• Team player