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Senior SoC/ASIC Design Verification Engineer

156225
San Jose, CA, United States
Dec 4, 2018

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Job Description

Description

This is an exciting opportunity to work in the Xilinx Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and silicon bring up.
 
Responsibilities:
-Create block level verification plan, test plans and full chip test plan
-Develop block level test plans.
-Develop block level test bench and tests in UVM methodology including scoreboard.
-Work on subsystem level verification 
-Work with designers to get the coverage closure
-Port the block level tests to full chip test bench 
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed.
-Work on other aspects of verification like CDC, gate simulation.
-Work on lab bring up and silicon validation.
 
 
 #mh


Education Requirements

Master's Degree in Electrical Engineering, Computer Science or related equivalent with 5+ years of experience Or

Bachelor's Degree in Electrical Engineering, Computer Science or related equivalent with 8+ years of experience 
 
Job Requirements:
 
-Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology.
-Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team 
-Good understanding of object oriented programming concepts.
-Familiarity with caching protocols such as MESI, MOSEI
-Familiarity with PCIE Express .
-Prior experience in verifying is system/sub system level involving multiple blocks.
 -Prior experience with protocols such as AXI, APB, AHB etc.
-Programming in scripting languages like Python, TCL and Perl.
-Excellent communication skills 
-Good problem solving skills and analytical ability
-Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.
 
Desirable Requirements:
-Prior experience in high speed serial protocols such PCIE and 10G Ethernet
-Prior experience with verifying snoop filters and directory based cache structures.
-Prior experience in verification of cache sub systems in processors and/or cache coherent interconnect such as CCI400
-Prior experience with coherent interfaces like IBM CAPI (Coherent Accelerator Processor Interface)
-Prior experience in working on caching protocols such as ACE and CHI.
-Prior experience in verifying is system/sub system level involving multiple blocks.
-Prior experience in verifying Multichip coherency.
 
-Exposure to formal verification methodologies
-Understanding of ARM architecture and assembly language programming
-Prior experience in integrating Verification IPs (VIP) & UVC in verification environment.
-Prior experience in bringing up gate level simulation and debugging issues.
 
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