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Senior Verification Engineer

156150
Hyderabad, India, India
Nov 14, 2018

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Job Description

Description

Job Summary:

 

    Xilinx is looking for a talented, self-driven and motivated engineer to be part of our IP Verification team in Hyderabad. This exciting position in the Xilinx IP Engineering group as Senior Verification Engineer will provide the individual with an opportunity to demonstrate technical leadership in verifying our next generation Ethernet and Interlaken solutions and also developing verification workflows and framework to test IP as delivered through Xilinx Vivado based IDE. Join us in developing Verification environment based on the industry standard UVM framework from scratch and drive high quality IP products that will be part of internal Xilinx Systems and high profile end customers

 

As a Senior Engineer you will work as part of a team responsible for all phases of product development and are expected to engage with product development team in India and other Xilinx Development Centers (US), Architect testbenches from scratch, Evaluate best possible options to develop the testbench and implement, Execute the verification development life cycle through well-defined convergence metrics of coverage(Code, Functional and Assertions), achieve performance by automation techniques and ensure a high quality IP generated for customer use.

 

Job Description for Verification Engineer:

  • B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 11+ years of relevant experience in IP verification and validation
  • Proven end to end verification of complex IP using System Verilog and latest methodologies which include UVM, OVM, VMM
  • Strong understanding and experience in verification of Ethernet protocols and IEEE 802.3 standards both MAC and PCS/PMA
  • Knowledge on Ethernet protocols and standards like 1588, Pause, FEC, RSFEC, AN/LT, TSN and speeds from 1GE upto 100GE
  • Knowledge on high speed serial transceiver GT and interface
  • Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
  • Proficient knowledge of System Verilog, HVL based methodology (UVM or OVM) and  hands on scripting experience for automation
  • Experience in verification including constrained-random, coverage driven verification environments
  • Strong debugging, verification and board validation skills
  • Should have handled verification of complex RTL designs and validating them on the boards
  • Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
  • Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus
  • Self-driven, motivated, result oriented individual with superior academic achievements
  • Excellent interpersonal, written, group communication and problem solving  skills
  • Good organizational and execution skills with ability to multi-task and prioritize

 

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