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Senior Design Engineer

156009
San Jose, CA, United States
Oct 10, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Oversees definition, design, verification, and documentation for ASIC development. Verify blocks and prove the functional correctness of Xilinx's next generation FPGA products. Develop test plans and coverage metrics from specifications. Write block and chip-level tests. Execute the test plans from start to finish. Debug RTL and Gate simulations and work with hardware and software development teams to verify fixes.


#LI-DNI

Education:
  • Master or foreign equivalent in Electrical Engineering, Computer Engineering, Computer Science or related field.
Experience:
  • 2 years experience as Design Engineer, Verification Engineer or related occupation.
Alternate Requirements:
  • Will also accept Bachelor’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, Computer Science or related field plus 5 years progressive experience in position or related occupation.
Special Requirements:
  • Must have at least 2 years of prior work experience in each of the following:
    1. Development of UVM or System Verilog or Verilog test benches 
    2. Usage of simulation tools/debug environments Synopsys VCS or Cadence IES.
    3. Perl, TCL/TK, and Shell scripting.
    4. Creating tests for verification in C/C++
    5. Verification management tools and database management particularly as it pertains to regression management.
    6. Protocols including AXI and DDR4.
    7. Gate level simulation, power verification, reset verification, contention checking, and abstraction techniques.
#LI-DNI
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