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Senior Design Engineer

155953
San Jose, CA, United States
Sep 28, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Define, verify, and documentation for ASIC development. Perform verification of next generation DSP processors in silicon. Work with a team of design and verification engineers on verification of a next generation DSP architecture in silicon. Work with architecture, design, and software teams to create block and sub-system level verification test plans and develop test cases for verifying next generation multi-core DSP processors. Create test benches, test plans, and test cases starting from the architecture and implementation specification. Work with architecture, design, verification and software teams to ensure micro-architecture and design are fully verified and validated across multiple platforms. Debug failures in simulation and emulation of the design on multiple platforms and support in identifying, obtaining, and verifying design changes.


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Education:

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.

Experience: 

• 2 years of experience as a R&D Engineer, Hardware Engineer, Technical Intern, or related occupation

Alternate Requirements:

• Will also accept a Bachelor’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and 5 years of progressive experience as R&D Engineer, Hardware Engineer, Technical Intern or related occupation.

Special Requirements: 

• Must have at least 2 years of prior work experience in each of the following:

1) Processor or SoC or IP Verification;
2) Architecting and developing self-checking constrained random verification environment using System Verilog and UVM Verification methodology; 
3) Debugging failures in RTL and verification environment on simulation platforms (including platforms using either Synopsys tools (VCS, etc), or Mentor tools (Questa, etc.);
4) Executing test plans, debugging failures, and improving coverage; and,
5) Perl or Python Scripting.

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