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Staff SOC Design Engineer

155921
San Jose, CA, United States
Oct 10, 2018

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Job Description

Description

 

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 

 

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

We have an opening for a Staff level Digital Hardware Design Engineer in the SOC Design team. In this highly visible role, you will work closely with SOC Architecture team, SOC Verification and Emulation teams and take direct design ownership of major functions of the SOC from Requirements to RTL to PD handoff. Your responsibilities will include Front End Implementation of your design.

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  • BSEE with at least 10 years of experience or MSEE with at least 8 years of experience with track record of multiple successful projects in 32nm and below with stringent schedule requirements
  • Expert level understanding of Verilog, SystemVerilog, Timing Constraints and Digital Design principles
  • Hands on experience of Front End Design and Implementation steps including Micro-Architecture, RTL Coding, constraints generation/verification/review, Lint check, CDC check, DC Synthesis and PT Static Timing Analysis.
  • ARM processor based SOC design experience
  • Experience with low-power/power-efficient designs
  • Experience with high speed (>GHz) design techniques
  • Experience with integrating multiple analog IP macros such as PHY, IO, PLL, SerDes
  • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
  • Simulation experience with Cadence IES and experience building block level verification suites
  • Understanding of DFT insertion techniques including SCAN, ATPG, MBIST and LBIST
  • Ability to develop clear and concise engineering documentation
  • Expert level understanding of AMBA protocols such as AXI, APB, ACE, AHB and CHI
  • Experience with automation using scripting techniques such as PERL, Python and TCL
  • Excellent verbal and written communication skills
  • Excellent organizational skills and attention to detail
  • Proficiency in Project Management concepts
  • Desired Experience
    • Working in design teams distributed over multiple sites
    • Post-silicon validation and debug
    • FPGA knowledge and emulation
    • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit
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