UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

CPU/DSP - Sr Staff Verification Technical Lead Engineer

155919
San Jose, CA, United States
Dec 3, 2018

Share:

Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

Xilinx FDST Verification group is looking for a Senior Staff Design Verification Engineer to provide technical leadership and contribution on SOC and IP designs. The individual will help design, develop and use simulation and/or formal based verification environments at block, full chip and SOC level to prove the functional correctness of the designs.
 
- The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on multiple high performance IPs and/or SOC designs.
- Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the design teams with an eye towards improving overall product quality.

#mh 

Job Requirements

  • Requires BS w/ 12+ yrs or MS 8+ yrs or PhD with 5+ yrs experience in Electrical Engineering, Computer Engineering, Computer Science or related equivalent.
  • Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES using multiple  VIPs.
  • Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
  • Develop and work with different verification platforms in SystemC/System Verilog including utilization of Emulation/Prototyping platforms for verifying next generation multi-core SOC designs.
  • Responsible for a comprehensive verification plan and to drive the implementation of verification test cases from applications and other sources.
  • Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc. is a plus
  • Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
  • Experience with FPGA programming and software is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with mixed-signal verification tools and methodology is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.
Share:
Refer to the Talent Network

Similar Jobs

System Validation Engineer

San Jose, CA, United States

Sr. Staff FPGA Characterization Engr.

San Jose, CA, United States

Serdes STA Engineer

San Jose, CA, United States

Serdes PHY Design Engineer

San Jose, CA, United States

Embedded Software Engineer

San Jose, CA, United States

Embedded Software Engineer

San Jose, CA, United States

Serdes Analog/Mixed Signal Design Engineer

San Jose, CA, United States

Validation Engineer

San Jose, CA, United States

SerDes Validation Engineer

San Jose, CA, United States

SerDes Architecture and Modeling Engineer

San Jose, CA, United States

Serdes PHY Design Engineer

San Jose, CA, United States

Senior SoC/ASIC Design Verification Engineer

San Jose, CA, United States

IT Merger & Acquisition Director

San Jose, CA, United States

Product Marketing Business Analyst

San Jose, CA, United States

Staff Software Engineer

San Jose, CA, United States

Corporate Counsel

San Jose, CA, United States

Tax Attorney - Mergers & Acquisitions

San Jose, CA, United States

Senior Director of Compensation and Benefits

San Jose, CA, United States

DSP Engineer

San Jose, CA, United States

Communications System Engineer - DPD

San Jose, CA, United States

Director of Web & Digital Design

San Jose, CA, United States