Memory Controller IP Verification (DDR, LPDDR, RLDRAM, QDR, HBM)
Xilinx FDST Verification group is looking for a Senior Design Verification Engineer to provide technical leadership and contribution on high speed Memory Controller IP Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, RLD, QDR, and HBM Memory Controller IP designs.
The ideal candidate is one who has hands-on experience with verification execution on Memory Controllers (DDR, LPDDR, RLDRAM, QDR, HBM), high performance IPs and/or SOC designs.
Require hands on experience with verification of state of the art memory controllers such as DDR, LPDDR, RLDRAM and QDR, and HBM. Requires understanding of current memory controller protocols and calibration (DDR3/4, LPDDR3/4, RLDRAM3, QDR2, QDRIV, HBM-Gen1/2), JEDEC specification, board skew and jitter modeling.
Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.