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Principal Design Engineer (Compiler Development)

155876
San Jose, CA, United States
Sep 10, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Oversee definition, design, verification, and documentation for Xilinx ASIC and tool development. Determine architecture design, logic design, and system simulation. Specifically, works on advanced development team responsible for building prototypes of next generation architectures and tools. Participate in the implementation of compilers, runtimes, drivers, debuggers, and parallel programming APIs for hybrid CPU+ FPGA computing systems. Perform application driven validation of the parallel programming frameworks and architectures, and benchmark area, performance, and power of parallel applications. Conduct prototyping of heterogeneous computing architectures. Lead customer workshops. Quickly understand complex customer requirements in novel wireless communication and image processing applications and propose custom FPGA-based hardware designs and compiler tools. Develop prototype hybrid CPU + FPGA designs (Designs generally consist of general purpose processors, special purpose processors, application specific FPGA or ASIC accelerators as well as customized interconnect and memory architectures). Prototype compilation and scheduling Tools for hardware accelerators that utilize automatic tiling, memory allocation and parallelization transformations. Involved in the development of languages, intermediate representations, and ABIs for vector, VLIW, and thread level parallel processor architectures. Inform and influence engineering decision-makers and advise the CTO on the direction of new compiler tools and architecture. Develop scheduling algorithms and constraint-driven compilation tools.


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Education:
  • Ph.D. or foreign equivalent in Computer Science, Computer Engineering, or related field.
Experience:
  • Three (3) years of experience as a Software Engineer or related occupation.
Special Requirements:
  • Must have experience, internship experience, or graduate academic training in the following:  
    1. Practical compiler development using the Polyhedral Model for memory scheduling or high level synthesis;
    2. Implementing FPGA designs requiring more than 100K LUTs (Look Up Tables) and  more  than  1K DSPs (Digital Signal Processing slices) using the Vivado High Level Synthesis tools;
    3. Computer architecture of ARM processors and AXI interfaces, including bare-metal programming and virtual memory systems;
    4. C++ and development of user-level libraries for Linux systems;
    5. Implementing and optimizing wireless DSP, video or image processing applications using parallel computer hardware and evaluating the compute performance of these applications; and, 
    6. Implementing hybrid designs which integrate processors, interconnect IP and FPGA-based logic in systems..
Other Requirements: 
  • 10% travel, fully reimbursed

#LI-DNI

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