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Design Engineer

155813
San Jose, CA, United States
Sep 5, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Job Description

  • Study architecture spec of blocks in processor subsystem to understand feature requirements at system level.
  • Develop design specification of the assigned function to include but not limited to feature description, interfaces, programming sequences, and integration requirements.
  • Develop RTL code in synthesizable SystemVerilog code to implement all required features efficiently.
  • Integrate design blocks from either external vendors or internal groups into the processor subsystem.
  • Ensure design meet internal design requirements, complying to good design practice and coding rules.
  • Create timing constraints to help implementation team to meet timing requirements.
  • Support functional debug and quickly resolve issues.
  • Support implementation team in quick timing closure, power reduction and meeting DFX requirements.
  • Support validation team in debugging prototyping systems or silicon.

Requirements:

  • BSEE + 2 years ASIC experience or equivalent.
  • Have taken classes in logic design, computer architecture, semiconductor device, and VLSI design.
  • Knowledge of SystemVerilog coding for synthesizable design.
  • Experience in debugging simulation results through waveform tracing.
  • Knowledge of file parsing with scripting languages.
  • Experience in using Design Compiler to synthesize at least one design with multiple clock domains to meet frequency requirements.
  • Good communication skills, both in conveying idea as well as accepting different idea.
  • Self-motivated and independent.
  • Knowledge of DFX is a plus.
  • Knowledge of AXI protocol is a plus.
  • Have published and reviewed design spec with peers is a plus.
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