Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
The verification team at Xilinx is looking for a Senior Design Verification Engineer to lead and contribute on the verification of Network On Chip IPs and Subsystems. The individual will help architect, develop and use digital simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network On-Chip (NOC) IPs, Subsystem, and SOC designs.
- Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specification
- Interact with architects and design engineers to create a comprehensive verification testplan
- Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
- Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Debug tests with design engineers to deliver functionally correct design blocks
- Identify and write coverage measures for stimulus quality measurements
- Perform coverage analysis to identify verification holes and achieve closure on coverage metrics
Candidate is expected to be a strong team player with good communication skills and one who is capable of working independently with an eye towards improving overall product quality.
- Degree in Electrical Engineering, Computer Engineering, Computer Science or related equivalent is required
- Requires BS w/ 5+ yrs or MS w/ 3+ yrs or PhD with work experience in pre-silicon design verification
- Understanding of state of the art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification
- Proficiency in System Verilog and UVM
- Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, Cadence IES or Mentor Questa is required
- Proficiency in Perl, Python and/or other scripting language
- Understanding of AMBA protocols like AXI4, AXI-STREAM and AHB is a strong plus
- Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus
- Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management is a plus