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Senior Design Verification Engineer (Contract)

155772
Singapore, Singapore, Singapore
Sep 25, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

This is an IC Design Verification Engineer position in the Hardware and System Product Develop on a contract basis to perform the following key activities
  • Develop and Review Test Plan based on design specification
  • Develop constrained-Random verification environment for complex DUT
  • Implement coverage matrix using cover point and assertion
  • Create and debug tests for DUT
  • Resolve bugs with remote designers

The successful candidate should possess/be at minimum

• 5 years of hands on experience with SystemVerilog/UVM

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering

• Strong understanding of verification process from test plan to coverage completion

• Strong communication and Analytical skills

• Understanding of HDL (Verilog, VHDL)

• Experience with designing with FPGA using Vivado is a plus

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