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Senior ASIC/SOC Design Engineer

155728
San Jose, CA, United States
Aug 10, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Xilinx has an opening for a Hardware Design Engineer in the SOC Design team. This team is designing the silicon portion of Adaptable Compute Acceleration Platform.

 

In this highly visible role, you will:

  • Own design and implementation of blocks to meet functional, timing, area and power requirements
  • Guide and review verification for blocks owned
  • Design and implement logic functions that enable efficient test and debug
  • Participate in silicon bring-up for features owned
  • Implement Automation to increase design team efficiency
  • Participate in build management

  • Required Qualifications
    • MSEE/CE with 2+ years of experience or BSEE/CE with 5+ years of experience or equivalent
    • Experience in designing blocks for an SOC
    • Experience in integrating ASIC IP into SOC
    • Experience writing timing constraints and exceptions in TCL or SDC syntax
    • Experience with automation using scripting techniques such as PERL, Python or TCL
    • Experience running standard quality checks such as Lint and CDC
    • Simulation experience and experience building block level verification suites
    • Experience with synthesis, static timing analysis & optimization
    • Ability to develop clear and concise engineering documentation
    • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
    • Excellent verbal and written communication skills
    • Excellent organizational skills and attention to detail

 

  • Desired Qualifications
    • Understanding of ARM architecture and APB, AXI, ACE, CHI protocols
    • Understanding of industry standard communication protocols such as PCIe
    • Experience running automated quality checks on timing constraints
    • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
    • Experience working in design teams distributed over multiple sites
    • Post-silicon validation and debug experience
    • FPGA knowledge and emulation experience
    • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit

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