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Staff HLS Software Engineer

155714
San Jose, CA, United States
Oct 10, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

You will be part of the SDx, which is the next generation software programming environment to enable application developers with little or no FPGA experience using high level programming languages, such as OpenCL, C and C++, to leverage the power of programmable hardware for application acceleration.

 

 

This position offers the opportunity to design and implementation of significant parts of SDx Compiler. You will get a chance to tackle many interesting and challenging problems on synthesizing designs from high level programming languages to cutting-edge Xilinx All Programmable architecture #hot  

#ik

  • MS in CS/CE/EE with 10+ years or PhD with 8+ years of high level synthesis product development experience 
  • Strong C++ programming
  • Familiarity with compiler intermediate representation design, front-end/middle-end/backend partition
  • Hand on experience in developing algorithms to generate optimized circuits base on high level description
  • Familiarity with digital design methodology,
  • Familiarity with mapping to Xilinx's FPGA
  • Familiarity with Xilinx FPGA implementation tool flow and timing closuring
  • Knowledge of computer architecture, especially memory subsystem
  • Experience with OpenCL or CUDA is a plus
  • Experience of LLVM/Clang and open source development is a plus

 

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