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Senior Verification Automation Design Engineer

155712
San Jose, CA, United States
Aug 1, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

 

Xilinx's SAV Verification group is looking for a motivated Design Verification Tools and Devops Engineer to contribute on verification infrastructure and devops. The individual will develop tools in python/perl/c for verification infrastructure and fix bugs with existing tool set.
 
Responsibilities:
•Use your expertise to design, build, test, monitor, manage and maintain tool-chains for critical functions as part of verification
•Own and drive improvements to our build, simulation, continuous integration, release scripts, tools, and process
•Bring new automation technologies to improve our existing flow and add new tool set for new emerging designs

Job Requirements
 
Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall productivity
 
•  Direct experience with ASIC standard verification tools, languages and flows
•  Strong working knowledge of one or more scripting languages including shell, Perl, Python, and/or Ruby
•  Strong background in object oriented programming
•  Excellent organizational and time management skills
•  Knowledge  using Verilog, System Verilog and UVM
•  Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management
•  Prior use of simulation tools/debug environments such as Synopsys VCS, Verdi or Cadence IES is a strong plus
•  Database administration and SQL/NoSQL
•  Continuous integration and deployment tools such as Jenkins
•  Used or familiar with using EDA in the cloud
•  Familiar with load sharing sw like LSF, Sungrid etc
•  Plus developing  web frameworks using PHP, Javascript, Python
•  Plus if familiar in using ML/AI for verification
   
  Education:
 
· BSEE with 6+ years or MSEE with 3+ years of relevant experience

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