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Data Center IP Staff Design Engineer

155700
San Jose, CA, United States
Sep 17, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

Xilinx is looking for an experienced and motivated leader to join the DataCenter

solutions, PCIe Connectivity, and Networking Acceleration engineering team.

As part of this team, you will play a key role in the design and implementation

of next generation FPGA-based intellectual property (IP) blocks for the cloud

scale-out data centers. IP includes Machine Learning, PCI Express, Multi-

Queue DMA, Networking Acceleration, and other protocols.

 

Come join us and be part of team that delivers world-class products that

set the industry standard for quality, ease of use and customer support. In

this role, you will have the opportunity to drive the design, verification, and

validation of FPGA hard IP blocks as well has companion soft solution IP block.

In addition you will work across the hardware/software boundary.

 

Education Requirements: Minimum of a BSEE/MSEE or related equivalent

Years of Experience: BS 8+ years, MS 6+ years or PhD 3+ years design experience

 

- Knowledge in multi-queue DMA and Networking implementations is a plus

- Experience with mirco architecture, design, and implementation of complex logic

- Experience with Verilog required

- Experience with FPGA design a plus

- Knowledge of PCIe, AXI, Networking protocols a plus

- Ability to quickly analyze and debug RTL issues

- Excellent oral and written communication skills

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