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Verification/Validation Engineer

155600
Hyderabad, India, India
Sep 4, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable adaptable, intelligent computing.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative and creative people to help deliver groundbreaking technologies that build an adaptable intelligent world. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


Responsibilities:
  • Develop test plan and coverage metrics based on the given IP Specifications.
  • Will implement testbench architecture, write tests, coverage/checker assertions.
  • Debug RTL as well as cross platform issues .
  • Work closely with the Design and Validation teams.
  • Validation on Emulation platforms like Palladium

 

Essential skillset: 
  • Expertise in Palladium ICE mode and validation/debug of issues on Palladium 
  • Should have experience of developing at least 2 module/chip level verification environments from scratch.
  • Experience in designing, verifying/validating AMBA bus based SOCs/IPs and ARM processors.
  • Hands on with at least one of the scripting languages like TCL, Perl or Python.
  • Strong understanding of atleast one Emulation platform like Palladium
  • Knowledge of Industry standard protocols like USB, SPI, QSPI, I2C, RGMII, Display Port
  • Strong debugging skills using FPGA, silicon and board level
  • Experience in developing the testbenches.
  • Object Oriented Programming Concepts.
  • Expertise in C/C++/SystemC programming.
Desirable skillset:
  • Experience with FPGA based design/verification methodology.

Education Requirements
  • BE/BTech (or higher) in EE/Computer Engineering.
Years of Experience
  • 6-8 years of design verification experience using HVLs like SV, UVM/OVM or Specman.
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