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FPGA Design Engineer

155598
Hyderabad, India, India
Oct 28, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable adaptable, intelligent computing.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative and creative people to help deliver groundbreaking technologies that build an adaptable intelligent world. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


Responsibilities:
  • Create FPGA based designs using Vivado
  • Prototyping of ASIC RTL to FPGA
  • Develop micro-architecture based on the given IP Specifications.
  • Do RTL coding, LINTing and sanity testing of the implemented design.
  • Work closely with the Verification and Validation teams to debug the issues.
Essential skill set
  • Strong understanding of Xilinx FPGA architecture
  • Experience in designing with AMBA Bus Protocol (AXI, APB) based SOCs/IPs and ARM processors.
  • Hands on with at least one of the scripting languages like TCL, Perl or Python.
  • Working knowledge of Vivado Synthesis
  • Scripting knowledge (TCL/Python/perl)
  • Experience in using timing constraints and Xilinx XDC
  • Knowledge of Industry standard protocols like USB, SPI, QSPI, I2C, RGMII, Display Port
  • Strong debugging skills using FPGA, silicon and board level
  • Experience in developing the testbenches.
  • Experience with FPGA based design methodology.

 Desirable skillset:

  • Knowledge/Working Experience with PCIe.

Education Requirements 
  • BE/BTech (or higher) in EE/Computer Engineering.
Years of Experience
  • 6-8 years of RTL Design experience using Verilog/SV.
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