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Senior STA Timing Design Engineer

155391
San Jose, CA, United States
Jun 14, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 

This STA position is in the Serdes Technology Group for an experienced Engineer to focus on synthesis and STA for SerDes. A brief description is as follows.

 

The successful candidate will be responsible for Design Implementation (Synthesis/STA/Timing closure) SerDes. The role will include driving and optimizing synthesis, power optimization, static timing analysis, and logic verification using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environment. The candidate is required to drive and enhance Synthesis, Static Timing and Power Optimization methodologies, for the STG  group.

 

 

 

 

 
• BSEE with at least 5-6 years of experience in ASIC implementation activities such as synthesis and STA.
•Top level and block level Synthesis and timing closure ownership high speed designs.
•Drive SoC timing budgets, develop timing constraints, power optimization, and timing closure sign-off activities.
•Work closely with digital, analog, and physical design teams to optimize for performance, power, and area.
•Drive low power implementation and optimization methodologies using UPF/CPF
•Drive Formal Verification (logic equivalency) flows for the designs Develop and maintain RTL-to-Netlist tool flows and methodologies.
•Good exposure to Synopsys tools such as design compiler, primetime and formality
•Good inter personal skills and able to interact well with other members in the functional teams of the business unit.
•Good communication skills.
Preferred Requirements:            
•Prefer 5-6 years of experience in ASIC implementation tasks.
•Participate in Library and Memory IP selection (bench-marking/evaluations), characterization, and configuration.
•Participate in SoC development planning and scheduling.
•Assist in the validation and debug silicon products in support of release to production.
•Experienced in automating flows. Good scripting skills (TCL/Perl/Python)
•Experienced in timing closure and sign-off activities with high speed IOs.
•Familiarity with physical design flows and assist the physical design team when required.
•Interact with tool vendors and debug tool related or IP related issues independently.
 
 
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