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Staff Design Engineer (DSP Architecture)

155350
San Jose, CA, United States
May 15, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Oversee definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation.  Implement the next generation DSP processors in silicon. Work with a team of architecture, design, and physical design engineers and contribute to the design and implementation of a next generation DSP architecture in silicon. Responsible for creating block level micro-architecture and design specification starting from the architecture specification; working with architecture, design, verification and physical design teams to ensure micro-architecture and design is robustly and optimally implemented in RTL; debugging failures in simulation and emulation of the design on multiple platforms and ensuring design is robust in functionality, performance and power; and exercising solid analytical problem-solving in troubleshooting component designs. Run and implement designs including debugging, digital and analog design, circuit design, RTL signal flow, basic TCL coding, and timing tools basics. Write code for devices and tools.
 
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Education:
  • Bachelor or foreign equivalent in Electrical Engineering, Computer Engineering, Information Technology or related field.
Experience:
  • 7 years progressive experience as Staff Engineer or related occupation. 
Special Requirements:
  • Must have at least 1 year of prior work experience in each of the following: 
    1. Micro-architecture design for control and data path blocks.
    2. RTL implementation skills using Verilog.
    3. Performance and power optimization techniques.
    4. ASIC design methodology for verification (Synopsys VCS).
    5. Defining test scenarios and creating block level test bench.
    6. Static Timing Analysis using PrimeTime and physical design CAD tools.
 
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