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Design Verification Engineer

155250
San Jose, CA, United States
Aug 8, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 
 
Xilinx’s SAV Verification group is looking for a Design Verification Engineer to contribute on high speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs.
 
Responsibilities:
  • Plan verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus quality measurements.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
 
 

Requirements:
Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.
  • Requires BS/BTech w/ 2 yrs or MS in Electrical Engineering, Computer Engineering or Computer Science.
  • Understanding of state of the art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification.
  • Proficiency in System Verilog and UVM.
  • Proficiency in C, Perl, Python and/or other scripting language.
  • Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management.
  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, or Cadence IES is a strong plus.
  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus.

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