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Design Verification Engineer

155249
San Jose, CA, United States
Jun 26, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

 
If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.
 
Xilinx’s SAV Verification group is looking for a Design Verification Engineer to contribute on high speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs.
 
Responsibilities:
  • Plan verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus quality measurements.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
 
Requirements:
Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.
  • Requires BS/BTech w/ 2 yrs or MS in Electrical Engineering, Computer Engineering or Computer Science.
  • Understanding of state of the art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification.
  • Proficiency in System Verilog and UVM.
  • Proficiency in C, Perl, Python and/or other scripting language.
  • Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management.
  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, or Cadence IES is a strong plus.
  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus.

Requires BS/BTech w/ 2 yrs or MS in Electrical Engineering, Computer Engineering or Computer Science.
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