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Senior STA Timing Engineer

155241
San Jose, CA, United States
Jul 23, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


Xilinx is seeking an experienced front end implementation engineer for the development of high-performance IP blocks in the company’s next generation product.  Successful candidates will be responsible for prototype implementation of assigned IP blocks to ensure RTL meets all defined quality metrics.  As a member of the Processor Systems Design group, you will work on both design flow automation and product implementation for tapeout.   Close interaction with both the RTL design team and signoff/backen-end implementation team is essential.  Responsibilities include SDC generation/verification, logic synthesis, running RTL LINT, DFT DRC, and CDC verification.  Additional responsibilities may include the development of power intent constraints (UPF), running LEC, Memory BIST insertion, and scan insertion.  Maximizing efficiency through the effective use of automation throughout these processes is expected.

                                                                                                                                                                                            


Applicants should possess a BS/MS in EE or equivalent field with applicable work experience in the several of the following tools.  The position requires substantial TCL-based scripting competence within CAD tool shell environments as wells as stand-alone TCL shell scripts.  Prior work experience in CAD, RTL, or front end implementation teams is expected. 

 

Required:

  • Strong TCL scripting background
  • Synopsys Design Compiler
  • PrimeTime experience including SDC constraint development for complex blocks with many clock domains

 

Optional Experience (experience with 2 or more of the following is desired):

  • Mentor Questa CDC (Zero In)
  • Spyglass LINT and DFT including the development of custom rules
  • Fishtail Confirm
  • Cadence Conformal LEC
  • Cadence Conformal Low Power including UPF development
  • Mentor Tessent Shell Memory BIST
  • Using databases such as Mongodb to store and query design metrics
  • Generation of HTML based dashboards with javascript functionality

 

Experience and Education:

  • Bachelor's degree or equivalent with eight years of experience, or a master's degree with six years of experience.

 

Highly motivated candidates with strong written and verbal communication skills and structured, well-organized work habits are desired.


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