DescriptionXilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.
Develop and implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
• Implement design from RTL to GDS on the most advance technology node.
• Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
• Bachelor/Masters Degree in Electrical/Computer Engineering
• Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing algorithms, with good understanding of UNIX/LINUX.
• Able to work autonomously as well as in a team environment across multiple geographical sites, with a strong desire to succeed.
• Excellent debugging, problem solving and analytical skills.
• Excellent verbal and written communication skills. Strong interpersonal skills.