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Principal Engineer, Design & Verification

154532
San Jose, CA, United States
Jul 9, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 

 

Job Description

Xilinx is looking for an experienced and motivated individual to join the Datacenter Solutions & IP team. As part of this team, you will play a key role in the design and implementation of next generation FPGA-based solutions focused on network acceleration including design and verification of programmable packet processing leveraging Xilinx SDNet technology and working on new network acceleration workloads.

You will be required to understand customer system level requirements and work with software and firmware teams to implement and verify complete system level solutions which includes both soft IP as well as FPGA hard IP blocks. Responsibilities include architecture development, design, simulation, verification, hardware validation, and documentation of scalable and configurable IP cores. #ik

 


BS/MS/Ph.D in CS/EE with more than 15 years of industry experience in high-speed networking/CPU/ASIC designs

In-depth expertise and knowledge of CPU/ASIC/ASSP architecture, microarchitecture, implementation and verification

Extensive experience with high speed logic design, timing and power optimization design techniques, Expertise in Verilog/VHDL RTL design and simulation, hardware debug and bringup is required

Expertise with FPGA architecture and software tools highly desired

Proven track record of successfully architecting and implementing major functional blocks in one or more chips in compute, networking and storage areas.

Expertise in SDN/NFV and  new trends in networking, storage and compute areas preferable

Working knowledge of programming languages (C/C++/Java) and scripting languages (Python/TCL etc) desired

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