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Principal Engineer, Design & Verification

154532
San Jose, CA, United States
Mar 16, 2018

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Job Description

Description

Xilinx Is The World's Leading Provider Of All Programmable FPGAs, SoCs And 3D ICs. These Industry-leading Devices Are Coupled With a Next-generation Design Environment And IP To Serve a Broad Range Of Customer Needs, From Programmable Logic To Programmable Systems Integration. Our All Programmable Devices Underpin Today's Most Advanced Electronics.

Xilinx programmable FPGAs and SoCs are becoming one of the leading devices of choice for serving the industry megatrends including Cloud, NFV, 5G and IoT.

The SDAccel development environment for OpenCL, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs.

The Software Defined Specification Environment for Networking (SDNet) in conjunction with Xilinx All Programmable FPGAs and SoCs allows for the creation of 'Softly' Defined Networks, a technology dislocation that goes well beyond today's Software Defined Networking (SDN) architectures.

 

Job Description

Xilinx is looking for an experienced and motivated individual to join the Datacenter Solutions & IP team. As part of this team, you will play a key role in the design and implementation of next generation FPGA-based solutions focused on network acceleration including design and verification of programmable packet processing leveraging Xilinx SDNet technology and working on new network acceleration workloads.

You will be required to understand customer system level requirements and work with software and firmware teams to implement and verify complete system level solutions which includes both soft IP as well as FPGA hard IP blocks. Responsibilities include architecture development, design, simulation, verification, hardware validation, and documentation of scalable and configurable IP cores. #ik

 


BS/MS/Ph.D in CS/EE with more than 15 years of industry experience in high-speed networking/CPU/ASIC designs

In-depth expertise and knowledge of CPU/ASIC/ASSP architecture, microarchitecture, implementation and verification

Extensive experience with high speed logic design, timing and power optimization design techniques, Expertise in Verilog/VHDL RTL design and simulation, hardware debug and bringup is required

Expertise with FPGA architecture and software tools highly desired

Proven track record of successfully architecting and implementing major functional blocks in one or more chips in compute, networking and storage areas.

Expertise in SDN/NFV and  new trends in networking, storage and compute areas preferable

Working knowledge of programming languages (C/C++/Java) and scripting languages (Python/TCL etc) desired

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