We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Senior Physical Design Engineer

Cork, Ireland, Ireland
Jul 13, 2018


Job Description


Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 

Senior Physical Design Engineer (Dublin or Cork - Ireland)


Xilinx are expanding their worldwide Physical Design team by creating new roles in the Cork and Dublin engineering teams. This is an exciting opportunity to come and contribute to the development of world class SerDes and RF DAC and ADC design activities taking place in Ireland. These Ireland based teams have won a number of prestigious industry innovation awards. These cutting-edge designs have also been presented at leading conferences and published in renowned technical journals.
Xilinx designs on leading edge 16nm and 7nm process nodes pushing the capabilities of the technology to the limits to continually improve product offerings. Xilinx utilises the latest CAD tools and methodologies to deliver on these latest nodes.  Candidates will work in a variety of disciplines related to the delivery of complex digital designs alongside an established Physical Design team based in Singapore.
Xilinx encourages employees to collaborate, learn and innovate to build on existing capabilities and explore solutions for future developments.


The successful candidate will have the following responsibilities

  • Develop and implement plans to synthesize, implement including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
  • Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
  • Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.

Qualifications and Experience

  • Bachelor/Masters Degree in Electrical/Computer Engineering 
  • 6 - 12 years of relevant experience
  • Good experience and knowledge in design flow from Netlist to GDS, Floor Plan, Synthesis, route , STA, CTS, RC Extraction and correlation
  • Static timing analysis, power and noise analysis and back-end verification across multiple projects. 
  • Proficient with backend design EDA tools Synopsys (preferred) or Cadence
  • Experienced in Design-For-Test tools (Tetramax, DFT Advisor) & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation).
  • Proficient in RTL design using verilog
  • Successfully track records of taping out complex SOC in 16nm and beyond.
  • Working knowledge of deep sub-micron routing issues as they relate to power and timing.
  • Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis
  • Self-motivated team worker, good verbal and written communication skills
Refer to the Talent Network