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Senior ASIC Design Engineer

154661
San Jose, CA, United States
Aug 16, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


Senior ASIC Design Engineer

Xilinx' design team seeks a candidate for design of a memory controller of latest cutting edge DDR technologies.

 

Responsibilities:

  • Writing documentation and specs
  • Writing RTL in Verilog
  • Interact with other engineering teams for physical design and software.
  • Contribute to methodology
  • responsible for all design analysis.for backend STA, CDC, Power. #ey

Qualifications:

  • Master's Degree in Electrical Engineering, Computer Engineering or related equivalent with 3+ years experience.
  • Demonstrated knowledge of DDR memory technology: DDR4/5. LPDDR3/4, HBM
  • Working knowledge of the definition of micro-architecture
  • Fluent with RTL Verilog and Hardware modeling
  • Ability to develop efficient, testable, scalable and well-documented RTL code
  • Experience with industry standard simulation, waveform debugging
  • Familiarity with synthesis, simulation, static timing, CDC-analysis
  • Understanding of logic low power design techniques and clock gating concepts
  • The individual should be knowledgeable of Verilog and SystemVerilog and familiar with scripting languages (Python, Perl) for automating solutions.
  • Good communication skills, self-motivation and teamwork are required 

 


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