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Senior IC Design Engineer

155016
San Jose, CA, United States
Mar 19, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 

Summary
 
We are looking for a seasoned design engineer Xilinx’s next generation high-speed memory PHY design within the IO, Clocking and Memory Sub-system group. The role requires architecting, design, and implementation of High-Bandwidth-Memory (HBM) interfaces for our next gen external memory solutions.
 
Responsibilities:
 
  • Digital design from micro-architecture development through to physical implementation and silicon validation
  • DDR and High-Speed PHY Design
  • Design Expertise in DDR4, LPDDR4, and/or HBM PHY and sub-system design
  • Work cross functionally with various groups from Marketing to Backend implementation and packaging to define the product and successfully implement #jm

 

 

Qualifications:
  • Master’s Degree in Electrical Engineering
  • 5+ years experience in ASIC Design, front-end RTL coding, complex state machine design
  • Demonstrative expertise in all phases of digital design techniques from micro-architecture development through to physical implementation
  • Experience with synthesis, STA, DFT, and standard ASIC design tools/flows
  • High-speed DDR PHYs such as DDR3/4 or LPDDR3/4 a plus
  • HBM experience is a plus

 

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