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Senior Verification Engineer

155118
San Jose, CA, United States
May 9, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 

Xilinx FDST Verification group is looking for a Verification Engineer to verify high speed SerDes designs.
 
The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs. Candidate is expected to be a strong team player with good communication skills and the motivation to excel.
 
The individual will have the following responsibilities:
  • Review design document and develop verification strategies for SerDes designs.
  • Develop verification plans and create block and chip level verification environments.
  • Create testcases to meet functional and code coverage goals
  • Debug failures in simulation and collaborate with designers in root-causing failures
  • Investigate methods to improve analog behavioral modeling for functional verification.
Qualifications:
  • Requires BS w/ 5+ yrs or MS 3+ yrs or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Requires experience with testbench development using verilog, systemverilog and UVM, 
  • Requires good OOP programming skills in languages such as C++, Python, Java or Systemverilog.
  • Requires good understanding of logic design and digital circuit fundamentals.
  • Coursework with strong performance or experience with DSP and Communication Systems is a big plus.
  • Coursework or experience in analog and/or mixed signal circuit design.


 












 

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