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Software Engineering Intern

155106
San Jose, CA, United States
Jul 11, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


SDAccel is the next generation software programming environment to enable application developers with little or no FPGA expertise to use high level programming languages, such as OpenCL, C and C++, to leverage the power of programmable hardware for application acceleration.

 

This position offers the opportunity to design and implementation of significant parts of SDAccel OpenCL compiler. You will get a chance to tackle many interesting and challenging problems working on compiler for cutting-edge FPGA hardware.


  • BS in CS/CE/EE with 2+ years or MS of compiler development experience 
  • Strong C++ programming
  • Familiarity with compiler intermediate representation design, front-end/middle-end/backend partition
  • Familiarity with Loop transformation and/or vectorization,
  • Familiarity with code generation from generic IR to target specific IR (e.g. machine code)
  • Familiarity with memory dependency analysis
  • Familiarity with building cost model at the compiler middle-end

Desired skills:

• Knowledge of LLVM/Clang and open source development

• Knowledge of computer architecture, especially memory subsystem

• Experience with OpenCL or CUDA is a plus

• Experience with Clang AST matcher and Clang tooling is a plus

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