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Software Engineering Intern

155106
San Jose, CA, United States
Apr 3, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

SDAccel is the next generation software programming environment to enable application developers with little or no FPGA expertise to use high level programming languages, such as OpenCL, C and C++, to leverage the power of programmable hardware for application acceleration.

 

This position offers the opportunity to design and implementation of significant parts of SDAccel OpenCL compiler. You will get a chance to tackle many interesting and challenging problems working on compiler for cutting-edge FPGA hardware.


  • BS in CS/CE/EE with 2+ years or MS of compiler development experience 
  • Strong C++ programming
  • Familiarity with compiler intermediate representation design, front-end/middle-end/backend partition
  • Familiarity with Loop transformation and/or vectorization,
  • Familiarity with code generation from generic IR to target specific IR (e.g. machine code)
  • Familiarity with memory dependency analysis
  • Familiarity with building cost model at the compiler middle-end

Desired skills:

• Knowledge of LLVM/Clang and open source development

• Knowledge of computer architecture, especially memory subsystem

• Experience with OpenCL or CUDA is a plus

• Experience with Clang AST matcher and Clang tooling is a plus

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