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Senior IO Applications Engineer

155103
San Jose, CA, United States
Nov 29, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


This position will be part of Silicon applications engineering team focused on advanced high speed FPGA I/O interfaces.  Job responsibilities include testing in hardware, building custom designs using Verilog or VHDL, creating application notes, datasheets and user guides. This position interfaces directly with silicon and software engineering groups, and is the primary interface between the engineering teams and escalated customer support issues. Strong background in RTL development and verification required. Experience in Silicon bring-up, hardware debug and customer interaction preferred. Proven track record of leading cross-functional projects is highly desirable.
 
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Qualification and Education Requirements 
 

  • BSEE or BSCE with 6-7 yrs experience or MSEE/MSCE with  5-6 yrs experience
  • Strong background in RTL development and verification
  • Experience in Silicon Bring-up and Hardware debug
  • Lab experience – familiarity with oscilloscopes, logic analyzers and basic debug techniques
  • Familiarity with programming/scripting language
  • Excellent written and verbal skills.
  • FPGA or ASIC design background preferred
  • Effective project planning and execution


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