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Senior HLS Engineer

154118
San Jose, CA, United States
Jun 25, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

 

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


You will be part of the SDx, which is the next generation software programming environment to enable application developers with little or no FPGA experience using high level programming languages, such as OpenCL, C and C++, to leverage the power of programmable hardware for application acceleration.

 

 

This position offers the opportunity to design and implementation of significant parts of SDx Compiler. You will get a chance to tackle many interesting and challenging problems on synthesizing designs from high level programming languages to cutting-edge Xilinx FPGA hardware. #hot #ey

 


 


 

  • BS in CS/CE/EE with 10+ years or MS with 8+ years of compiler development experience 
  • Strong C++ programming
  • Familiarity with compiler intermediate representation design, front-end/middle-end/backend partition
  • Familiarity with Loop transformation and/or vectorization,
  • Familiarity with code generation from generic IR to target specific IR (e.g. machine code)
  • Familiarity with memory dependency analysis
  • Familiarity with building cost model at the compiler middle-end

Desired skills:

• Knowledge of LLVM/Clang and open source development

• Knowledge of computer architecture, especially memory subsystem

• Experience with OpenCL or CUDA is a plus

• Experience with Clang AST matcher and Clang tooling is a plus

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