Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.
If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.
Job Summary :
This exciting position in the Xilinx IP Engineering group as the high speed link u-architect and lead designer will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation high speed serial link IP solutions. Join us in providing innovative IP solutions as we embark on our journey in providing world class high speed link designs running at well over 25Gbs for Xilinx All Programmable FPGA platforms
As a Senior Staff Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Senior Staff Design engineers are expected to participate in and lead all aspects of technical projects including: new product exploration, evaluating emerging technologies, working closely with Product marketing managers and end customers, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization
This position requires the individual to be creative, team-oriented, technology savvy, able to u-architect and lead complex designs given a high level architecture and willing to directly work with customers on new product definition
A major part of your responsibility will be to take a lead technical role in all phases of the product development cycle from architecture through implementation, prototyping, validation and support including:
- Evaluating emerging technologies and identifying the FPGA opportunities in the domain of high speed link design
- Be the main liaison from the IP engineering team to the high speed IO design team and be the local high speed link design expert
- Contribute to new architectures, usually within an established strategic direction
- Evaluating and executing design and development plans for IPs
- u-Architecture, design, documentation, prototyping
- Participating in and acting as a senior technical reviewer for various architecture and implementation reviews within the development organization
- Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
- Defining work required to design, implement and test new products. Identifies problems well in advance and proposes solutions
- As technical leader of a team, you will act as a technical advisor and resource to other engineers
- Critically Review and provide feedback on the Design Implementations and Verification plans
- Acting as technical advisor to engineering management #hot
- Strong oral and written communication skills are essential
- Ability to work collaboratively with other engineers and have strong influencing and leadership skills
- Detailed understanding and proven track record of developing leading edge standard and proprietary high speed interfaces like PCIe, Ethernet
- Good understanding of high speed IO design aspects and its impact on digital design
- Clear understanding of physical layer to IO interface and familiarity with best known practices to keep this interface clean and simple
- Experience in system level validation and debug of high speed interfaces
- Familiarity with electrical challenges that come with high speed link design
- Detailed knowledge of PCIe is a plus
- Experience with high speed link designs above 10Gbps line rate is a plus
- The ideal candidate will be a proactive contributor and subject matter expert
- Ability to effectively communicate with customers about existing and new product directions and technology.
- Individual must work effectively with Director and Senior Director level employees within the function, across functions and with external parties.
- To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.
- Contributes, explicitly or by example, to the standards and processes used by Xilinx or product development.
Education and Experience :
- A minimum of 10 years of experience is required.
- A Bachelor of Science Degree in Electrical Engineering or Computer Science, a Master Degree, or a PhD; or equivalent experience is required.
- Demonstrated ability to have completed multiple, complex technical projects.
- Demonstrated ability to provide technical advice, leadership, and direction to more junior engineers.